IEEE 2013 / 2014. Final Year Academic projects ECE / EEE / EIE/ Civil and International Journals--Call Us +91 40 4261 5556/7,2315 8786, 69995758 or mail Us: info@abhyaasprojects.com >> Please find the Updated list 2013 at our campus. <<
IEEE 2013 / 2014 Final Year Academic projects ECE / EEE /Civil and International Journals.As the cost of projects have increased due to increase in budjet and other categories, please confirm the Price before depositing.

Design of Low Power TPG Using LP-LFSR

This project presents a novel test pattern generator which is more suitable for Built In Self Test (BIST) structures used for testing of VLSI circuits. The objective of the BIST is to reduce power dissipation without affecting the fault coverage. The proposed test pattern generator reduces the switching activity among the test patterns at the most. In this approach, the single input change patterns generated by a counter and a gray code generator are Exclusive–O Red with the seed generated by the low power linear feedback shift register [LP-LFSR]. The proposed scheme is evaluated by using, a synchronous pipelined 4×4 and 8×8 Braun array multipliers. The System-On-Chip (SOC) approach is adopted for implementation on Altera Field Programmable Gate Arrays (FPGAs) based SOC kits with Nios II soft-core processor. From the implementation results, it is verified that the testing power for the proposed method is reduced by a significant percentage.

 

LANGUAGE USED:

  • VHDL/VERILOG

 

TOOLS REQUIRED:

  • MODELSIM – Simulation
  • XILINX-ISE – Synthesis

 

This content is password protected. To view it please enter your password below:

This content is password protected. To view it please enter your password below:

This content is password protected. To view it please enter your password below:

This content is password protected. To view it please enter your password below:

Coming Soon…

Coming Soon…

 
Comments

No comments yet.

Leave a Reply

You must be logged in to post a comment.